1. Field of the Invention
The present invention relates to a control device for writing display data in a memory, which is used, for example, in an electronic device having a liquid crystal display section.
2. Description of the Related Art
FIG. 5 is a diagram showing the structure of a conventional display control device having a display video memory (VRAM) in a system memory. The system memory 13 is connected to a central processing unit (CPU) 11 via data and address bus 12, and also segment display drivers (D/D.sub.SEG) 15a and 15b of a dot matrix liquid crystal display 14 are connected to the CPU 11.
The CPU 11 includes a liquid crystal display control section 11a, control signals from which are supplied to the system memory 13, D/D.sub.SEG 15a and 15b, as well as to a common display driver (D/D.sub.COM) 16.
In the conventional display control device shown in FIG. 5, the VRAM 13a is provided in the system memory 13, and the VRAM 13a in the system memory 13 is directly accessed by the CPU 11 for writing/reading of data to be displayed. Therefore, the software burden can be reduced. However, while data is displayed on the LCD 14, the display data in the VRAM 13a must be transferred at all times to the D/D.sub.SEG 15a and 15b, and therefore when the number of display pixels is increased, the data transfer amount, that is, the number of times of data access to the VRAM 13a, is accordingly increased, resulting in consuming a great amount of current.
FIG. 6 is a diagram showing the structure of another conventional display control device comprising a display video memory (VRAM) in a display driver chip. As shown in the figure, a system memory 23, a liquid crystal display section 24, and segment display drivers (D/D.sub.SEG) 25a and 25b are connected to a CPU 21 via data and address bus 22.
Display data and a write control signals for VRAMs 26a and 26b respectively provided in the D/D.sub.SEG 25a and 25b are supplied to the D/D.sub.SEG 25a and 25b from the CPU 21, and a display timing signal from a liquid crystal display control section (LCDC) 27 provided in the D/D.sub.SEG 25a is supplied to the D/D.sub.SEG 25b and a D/D.sub.COM (common display driver) 28.
More specifically, in the conventional display control device shown in FIG. 6, while data is displayed on the LCD 24, a segment of the LCD 24 is driven directly by the bit pattern data written in the VRAMs 26a and 26b in the D/D.sub.SEG 25a and 25b, and therefore even if there are a great number of display pixels, the number of times of data access with respect to the CPU 21 can be kept small. Further, since a multi-bit output memory can be used as a memory for display, the current consumed can be made small.
However, when the number of system buses 22 from the CPU 21 to the D/D.sub.SEG 25a and 25b is reduced in designing for the purpose of the downsizing of device, the accessing of the CPU 21 to the D/D.sub.SEG 25 in terms of processing of command, address and display must be carried out by software control. As a result, this display control device entails the problem of a heavy software designing burden as compared to the conventional display control device comprising the VRAM in the system memory, shown in FIG. 5.
In short, one type of the conventional display control devices has the problem of a large consuming current due to the data access to the VRAM 13a in the system memory, and the other type has the problem of a heavy software burden due to the data access with respect to the CPU 21.